FPGA Interview questions

http://fullchipdesign.com/fpga_interview_questions.htm

Q. Explain CLB’s, LUT’s of FPGA’s ?
Hint: LUT’s, CLB’s or PLB’s discussion next:
FPGA Look UP Tables (LUT).
LUT is a multi input and single output block that is widely used for logic mapping in truth-table format. A LUT can use various size RAM blocks to store logic. 
FPGA PLB’s or CLB’s.
A typical layout of the FPGA is an array of interconnected programmable Logic Blocks(PLB) or configurable logic blocks (CLB).  A PLB or CLB can itself consists of multiple LUT’s, one or more of Adders and many Registers.

Q. What information from the targeted fpga device is required in RTL synthesis? Hint: Device/part number, Speed grade etc. Device options :- part number, technology, package, Speed grade etc. Mapping options:- resource_sharing 1 (for On) frequency 10.000 (10 MHz operation) fanout_limit 10000 pipe 1 retiming 1. Many more options are possible and they are dependent on technology. 

Q. During which part of the fpga flow you specify the clock frequency for the design? Hint:- Both synthesis and layout..  
Q. How to constrain async clock crossing paths in design?
Hint:- False path it. No need to specify timing information for these paths.  
Q. How to control resets de-assertion in design when clocks are generated from PLL’s on fpga? Hint:- Logical ‘AND ‘of external hardware reset and PLL lock signal.

Q. What kind of sanity checks are good to look for in rtl synthesis logs? Hint: Look for latches, feedback-mux’s, combinational loops, tristate logic, black boxes etc. 

Q Can clock gating cells (latch based) for a design targeted for ASIC can be ported to FPGAs? Hint: Maybe, use fpga specific functions. Altera FPGAs use ALT_CLKCTRL block for clock gating. Its also used for clock multiplexing.

Q. How to implement synchronous Memory implementation to infer FPGA sync RAM blocks. Hint: Access following link.
  Q. What kind of sanity checks one should do from Place and route logs? 
Hint: 
1. Look at the design utilization. 2. Look for unconnected IO’s. 
3. Timing report should not have any failing paths. No setup and hold violations.

Q What are the different fpga flow’s primarily used in industry?
Hint: Altera, Xilinx, Lattice Semiconductor,  etc.  
Q what are different Programmability options for FPGA’s? Hint: SRAM based - Xilinx, altera Antifuse based- Actel, Quicklogic EPROM/EEPROM based- Not commonly used

Q What are major differences in SRAM and Antifuse Programming? Hint: Anti-fuse: non re-programmable, high speed, low area. SRAM based: re-programmable, more delay, more area.